Who uses PULP

This is the list of technology companies, NGOs and academic institutions that currently use PULP. Does your company or institution use PULP? Please, contact us. We would love to add you to our list.

Industrial users


Open HW group is a new not-for-profit global group that aims to boost the adoption of open-source processors. PULP Platform is proud to contribute to the Core-V family of cores by OpenHW group.

lowRISC works in close collaboration with PULP and uses PULP's components and processor cores. Explore more on GitHub.



Google has been using our RI5CY for Pixel Visual Core, highlighting its SolderPad license and SystemVerilog implementation. For more information watch this video and slides by Matt Cockrell at the RISC-V workshop 2018 in Barcelona.

IBM has been using our 32-bit PULPino as a starting point for their Next-Generation Edge Computing project, as presented at the RISC-V workshop 2018 in Barcelona. See the slides and the video from the talk by Seiji Munetoh.

NXP has been collaborating with PULP Platform on our 32-bit PULPino. See the slides and the video from the talk by Rob Oshana at the RISC-V workshop 2018 in Barcelona.

GreenWaves Technologies developed a fully-programmable near-sensor analytics IoT application processor GAP8 based on our PULP. Learn more about GAP8 on their website. and from this presentation by Eric Flamand.

STMicroelectronics collaborated with PULP platform to showcase their FD-SOI technology. More on this can be found in the paper 'Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster'.

GLOBALFOUNDRIES has a direct collaboration agreement with PULP for exploring design methodologies in their 22 FDX technologies. A joint presentation with PULP can be found here.

Embecosm has been using PULP cores in their projects. They have made several contributions to fix issues in our cores and forked our RI5CY for Verilator and GDB server development.

Dolphin Integration, a leader in energy-efficient IPs is using an adapted version of our Zero-riscy in their RISC-V subsystem called RV32 Tornado. Read more about it on their website.

CEVA-DSP, the licensor of signal processing platforms and IoT processors, started using our Zero-riscy to offer turnkey hardware platforms with FreeRTOS and communication stacks running on it. Find out more.

IQ-Analog taped out a GLOBALFOUNDRIES 14nm ADC/DAC test chip with a RI5CY core+ 256K instruction and 128K data SRAM. There seems to be a follow-up with 2 RI5CYs, as well. Learn more.

Mentor uses our PULPino microcontroller system because it allows them to showcase their tools without being encumbered by licensing restrictions.

Cadence uses PULPino as a reasonably-sized design for their training modules for their EDA tools without having to worry about license restrictions.

QuickLogic collaborates with ETH Zurich on eFPGA integration into PULP platform. The fully integrated system with eFPGA is expected to be available Q1' 2019. Learn more

OneSpin Solutions uses PULPino to demonstrate EDA products, for customer training and to test the RISC-V Integrity Verification Solution.


Imperas offers RISC-V Open Virtual Platform Simulator (riscvOVPsim) for RISC-V software development and compliance testing, supporting also our RISC-V cores.


Silicon Labs works with PULP to extend the functionality of processor cores for deeply embedded heterogeneous applications. They have a uC/OS version for RISC-V and planned a port to the PULP platform.

Axiomise is a vendor-neutral formal verification training, consulting & services company. They use the PULP platform to help verify some of the RISC-V cores for the PULP team.

Ashling provides a comprehensive tools solution for PULP RISC-V based cores, including C/C++ cross-compiler support for any RISC-V ISA with custom extensions. Learn more.

ACP uses PULP-derived cores in their new generation of RF SoCs for cellular IoT products.



Valtrix recently enabled their IP/SoC verification platform on the open source test bench of PULPino. Learn more.


Antmicro implemented preliminary support for the VEGA board with RI5CY capable of running Zephyr in their open source Renode simulation, continuous integration and software testing framework.

WITTENSTEIN high integrity systems has developed RISC-V port for their SAFERTOS, targeting VEGAboard, which supports our RI5CY and Zero RISCY (Ibex) core. Learn more.

Thales contributed to the ARIANE core, and continues its open source participation within the OpenHW Group which hosts the CORE-V cores inherited from PULP.


Semidynamics a European supplier of RISC-V IP cores specializes in high bandwidth HP cores with vector units for ML and AI applications. SemiDynamics has been using PULP components in some of its designs.

HENSOLDT Cyber MiG-V general purpose logic-encrypted processor is based on our 64-bit, 6-stage Ariane. Hensoldt's processor is targeting high-security applications.


3db Access has integrated PULPissimo RISC-V in its dual mode IEEE 802.15.4z UWB SoC for Secure Ranging and Localization.

Rhea, SIPEARL's implementation of the EPI platform will include a PULP instance in the power management unit.

The MAX78000 low-power neural network accelerated microcontroller from Maxim Integrated combines a CNN and a RISC-V core inspired by PULP.

TESDA develops a SoC design verification automation tool TESDA explorer. They employ PULP to create complex large heterogeneous SoC hardware to demonstrate the capability of TESDA explorer.

Synthara integrates several PULP cores in its low-power and high throughput AI accelerators to increase their flexibility and ensure compatibility even with the most sophisticated algorithms.


EGGTRONIC integrates a PULPissimo based system as core of a mixed-signal integrated controller for cutting edge power conversion and wireless power architectures.


SIAE Microelettronica is evaluating PULP clusters as accelerators for their next-generation communication systems.


Research institutions

Fraunhofer collaborates with PULP in diverse areas, such as the development of a sensor platform for individually configurable IoT and edge computing solutions for SMEs.

IMEC uses PULP-based systems to evaluate solutions for 3D stacking of ICs, as well as to develop ML accelerators around PULP architectures.


CEA collaborates with PULP on various projects, such as European Processor Initiative or the proof-of-concept SamurAI chip that couples a low-power IoT node with an energy-efficient ML accelerator.


Direct academic collaborators on PULP

  • Politecnico di Torino
  • University of Cambridge
  • USI Lugano
  • TU Kaiserslautern
  • IBM Research Zurich
  • EPF Lausanne
  • CSEM Neuchatel
  • Princeton University
  • Technische Universität Graz
  • Sapienza Università di Roma
  • University of Cagliari
  • Bar-Ilan University

Other academic users

  • Università di Genova
  • Politecnico di Milano
  • Fondazione Bruno Kessler
  • Lund University
  • Stanford University
  • UC Los Angeles
  • UC San Diego
  • Columbia University
  • İstanbul Teknik Üniversitesi
  • NCTU Hsinchu
  • University of Zagreb, FER
  • TUT Tampere
  • RWTH Aachen
  • IST University of Lisboa
  • UFRN Rio Grande do Norte
  • TU Darmstadt
  • Universität Bremen
  • Hongik University Seoul
  • IIT Kharagpur
  • LIRMM Montpelier
  • University of Stuttgart
  • University of Tübingen
  • TU Münich
  • FORTH Hellas
  • Kyoto University
  • Tecnologico de Costa Rica
  • Chalmers Göteborg
  • NTNU Trondheim
  • IDSIA Manno
  • FAU Erlangen-Nürnberg
  • TU Dresden
  • SVNIT Surat

Start-ups / SMEs

  • SoC HUB Tampere