Coming Q1 2018
HERO is our open-source, FPGA-based heterogeneous SoC research platform that combines a fully modifiable RISC-V manycore accelerator with an ARM Cortex-A host processor.
In addition to a silicon-proven RISC-V manycore accelerator, HERO includes:
- a heterogeneous software stack that supports OpenMP 4.5 and Shared Virtual Memory for transparent accelerator programming,
- a cycle-accurate, non-interfering event tracing infrastructure complemented by a flexible event analysis and profiling framework,
- an automated implementation and validation solution that enables efficient research and development on all software and hardware layers.