General questions on PULP/PULPino
PULP stands for Parallel Ultra Low Power platform, but it’s also a homage to a certain movie by one Tarantino 😉
Therefore, the correct pronunciation of PULP is that of the English word “pulp”.
PULPino is PULP plus the Italian diminutive “-ino”, it thus means “small PULP”. Its pronunciation is “pulp-in-o”.
PULPissimo is PULP plus the Italian superlative “-issimo”, it sort of means “the most PULP”.
We might manufacture more PULP chips in the future.
- Gloabalfoundries 22nm FDX
- ST Microelectronics 28nm FDSOI (both RVT and LVT)
- GlobalFoundries 28nm SLP
- TSMC 40nm LP
- UMC 65nm LL
- SMIC 130nm
- EM-Marin ALP 180nm
Licensing and Open-Source Questions
Most development tools we developed and software that runs on the PULP platform is released under liberal open-source licenses such as 3-clause BSD. Specialized toolchains and debug tools based on GCC are copyright of the Free Software Foundation and released under the GNU GPLv3 license.
Also, we ask you to cite the relevant scholarly publications (see ETHZ PULP page and Unibo PULP page).
In addition, having a stable processing platform could help a number of small startups and SMEs to designing their own products/ICs, by reducing engineering costs. This is important, as these companies are potential employers for our graduates and we have an interest to support SMEs working on IC Design.
It is a relatively small design that easily fits on a cheap FPGA board such as a ZedBoard and can thus be used in a variety of cases where a big FPGA is too expensive (think of teaching classes!).
Finally, there are many applications where you would need a small and efficient microprocessor that will not demand a very large workload, e.g. as a small microcontroller integrated within a bigger system-on-chip. PULPino provides a ready-to-use, open source microcontroller IP that can be integrated within such designs.
- RI5CY. DSP enabled 4-stage pipeline core with custom PULP extensions
- Standard configuration (like our previous releases)
- RI5CY + FPU includes an IEEE-754 compliant FPU
- Zero-riscy, 2-stage pipeline RISC-V core optimized for small area
- Zero-riscy, standard RV32ICM implementation
- Micro-riscy, extra small implementation, 16 registers (RV32E), no hardware multiplier
- Hardware loop instructions for more efficient loop handling;
- Post-increment memory instructions allowing to update pointers more efficiently;
- DSP like instructions enabling very energy-efficient signal processing
These can be used with the toolchain that we have customized for these functions.
For what concerns synthesis for ASIC targets, we mainly use Synopsys Design Compiler but we expect other synthesis tools to work as well, provided that they support SystemVerilog.