PULPino datasheet

This document contains the full documentation for the PULPino platform.

RI5CY core user manual

This document contains the full documentation for the RI5CY core.

Zero-riscy core user manual

This document contains the full documentation for the zero-riscy core.

HPCA2018 Slides

Complete slide set from our workshop in HPCA 2018 Vienna. Talks on PULP family, Cores, Accelerators and Programming.

PULPino processors features
1 Custom toolchain based on GCC 5.2; Using -O2 -g -falign-functions=16 -funroll-all-loops
Core Configuration RI5CY RI5CY+FPU Zero-riscy Micro-riscy
ISA Support RV32IMCXpulp RV32IMFCXpulp RV32IMC RV32EC
Interrupts Vectorized + Nested Vectorized + Nested Vectorized + Nested Vectorized + Nested
Debug Run, Control, Inspect Run, Control, Inspect Run, Control, Inspect Run, Control, Inspect
Enhanced instructions Hardware Loops, Post-Increment LD/ST, Bit Manipulation, Fixed Point, Packed-SIMD Hardware Loops, Post-Increment LD/ST, Bit Manipulation, Fixed Point, Packed-SIMD None None
Performance [CoreMark/MHz] 3.191 3.191 2.441 0.911
PULPino processor implementation data1
1 Target frequency at the back-end: 100 MHz (slow frequency), worst conditions, 125°C, 1.08V in UMC 65nm. Numbers in the table show typical conditions, 25°C, 1.2V results
Core Configuration RI5CY RI5CY+FPU Zero-riscy Micro-riscy
Area [Kilo Gate Equivalent] 40.7 69.3 18.9 11.6
Frequency [MHz] 185 - 185 185
Dynamic Power Density [μW/MHz] 5.07 - 2.08 1.88
Leakage Power [μW] 1.91 - 0.73 0.45
FPU performance1
1 The PULPino maximum frequency w/o FPU is ~410 MHz and ~370 MHz w FPU (WC, 125°C 1.08V UMC65)
Instruction Latency Throughput Architecture
Addition/Subtraction 2 1 Fully pipelined
I2F 2 1 Fully pipelined
F2I 2 1 Fully pipelined
Multiplication 2 1 Fully pipelined
FMAC 3 1/3 Iterative
DIV/SQRT 8 1/7 Iterative

Presentation at the 5th RISC-V Workshop

Presentation at the 4th RISC-V Workshop

Slides from RISC-V Workshop, 2016.

Presentation at the 3rd RISC-V Workshop

Slides / poster from RISC-V Workshop, 2016.

Presentation at ORCONF 2015

Slides from ORCONF, 2015.