As PULP and PULPino are first and foremost a platform for research, here you can find a list of our scholarly publications (up-to-date as of July 2016). Wherever this is possible, they are available as green open access publications, i.e. you can download the self-archived copy directly from this website.

Michael Gautschi, Davide Rossi, Luca Benini
Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory
Proceedings of the 24th edition of the great lakes symposium on VLSI (GLSVLSI 2014)

Davide Rossi, Igor Loi, Germain Haugou, Luca Benini
Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters
Proceedings of the 11th ACM Conference on Computing Frontiers (CF 2014)

Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI
The 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2014)

Igor Loi, Davide Rossi, Germain Haugou, Michael Gautschi, Luca Benini
Exploring Multi-banked Shared-L1 Program Cache on Ultra-Low Power Tightly Coupled Processor Clusters
Proceedings of the 12th ACM Conference on Computing Frontiers (CF 2015)

Michael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta
Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores
2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2015)

Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
Power, Area, and Performance Optimization of Standard Cell Memory Arrays through Controlled Placement
ACM Transactions on Design Automation of Electronic Systems (TODAES) DOI 10.1145/2890498

Davide Rossi, Antonio Pullini, Michael Gautschi, Igor Loi, Frank Gürkaynak, Philippe Flatresse, Luca Benini
A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2015)

Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Gürkaynak, Andrea Bartolini, Philippe Flatresse, Luca Benini
A 60 GOPS/W, -1.8V to 0.9V Body Bias ULP Cluster in 28nm UTBB FD-SOI technology
Elsevier Journal of Solid State Electronics (JSSE), DOI 10.1016/j.sse.2015.11.015

Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Philippe Flatresse, Luca Benini
PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications
HOTCHIPS 2015

Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro-Panades, Edith Beignè, Fabien Clermidy, Faby Abouzeid, Philippe Flatresse, Luca Benini
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V Voltage Range Multi-Core Accelerator for Energy Efficient Parallel and Sequential Digital Processing
COOLCHIPS 2016

Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
Energy-Efficient Vision on the PULP Platform for Ultra-Low Power Parallel Computing
2014 IEEE Workshop on Signal Processing Systems (SiPS 2014)

Davide Rossi, Antonio Pullini, Igor Loi, Francesco Conti, Giuseppe Tagliavini, Andrea Marongiu
Energy efficient parallel computing on the PULP platform with support for OpenMP
2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel (IEEEI 2014)

Manuele Rusci, Davide Rossi, Michela Lecca, Massimo Gottardi, Elisabetta Farella, Luca Benini
An Event-Driven Ultra-Low-Power Smart Visual Sensor
IEEE Sensors Journal 16, DOI 10.1109/JSEN.2016.2556421

Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision
Springer Journal of Signal Processing Systems (JSPS), DOI 10.1007/s11265-015-1070-9

Francesco Conti, Luca Benini
A Ultra-Low-Energy Convolution Engine for Fast Brain-Inspired Vision in Multicore Clusters
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE 2015)

Michael Gautschi, Michael Schaffner, Frank Kagan Gürkaynak, Luca Benini
A 65nm CMOS 6.4-to-29.2 pJ/FLOP@ 0.8 V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster
2016 IEEE International Solid-State Circuits Conference (ISSCC 2016)

Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank Kagan Gürkaynak, Luca Benini
High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE 2016)

Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
A Heterogeneous Multi-Core System-on-Chip for Energy Efficient Brain Inspired Vision
Late Breaking News of ISCAS 2016

Pirmin Vogel, Andrea Marongiu, Luca Benini
Lightweight Virtual Memory Support for Many-Core Accelerators in Heterogeneous Embedded SoCs
Proceedings of CODES+ISSS 2015

Francesco Conti, Daniele Palossi, Andrea Marongiu, Davide Rossi, Luca Benini
Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE 2016)