General questions on PULP/PULPino

It is a silicon-proven parallel platform for ultra-low power computing targeting high energy efficiencies. The platform is organized in clusters of RISC-V cores that share a tightly-coupled data memory. It consists of a set of IPs described in the SystemVerilog hardware description language (HDL), the related simulation and synthesis scripts as well as the runtime software (written in C and RISC-V assembly) to enable using the platform.
PULP stands for Parallel Ultra Low Power platform, but it’s also a homage to a certain movie by one Tarantino 😉
Therefore, the correct pronunciation of PULP is that of the English word “pulp”.
PULPino is PULP plus the Italian diminutive “-ino”, it thus means “small PULP”. Its pronunciation is “pulp-in-o”.
PULPino is already available, we are hoping to release the multi-core PULP platform soon. (see our Release Plan). Our plan is to eventually release everything we have developed through this website.
While we deeply believe in open-source hardware, we do not want to release a platform that we do not feel is ready. Part of the PULP platform is still in heavy development and is not in a state that would allow a world-wide distribution yet. For this reason, we started by releasing the most mature IPs, instantiated in the PULPino project. Nonetheless, we are open to research collaborations using the full PULP platform even at this stage.
PULPino contains only a single RISC-V core, there is no multi-core support. This also means that most of the memory and cache sharing infrastructure in PULP is not needed for PULPino. PULPino contains most of the interfaces we have developed throughout the PULP project and is a complete microprocessor system that can be used directly.
At the moment, we are not planning to make a production run of PULP/PULPino, we will have a few (<50) chips from the recent MPW runs and we plan to have at least some of them running on a small development board, that we plan to make available to our project partners.
We might manufacture more PULPino chips in the future.
Yes, you can. However, there will be some work involved. We cannot release any technology specific views and information, so you will need to adjust the code to instantiate the appropriate SRAM (or Flash) macros, I/O cells and clocking solution (PLL/FLL) for the technology you are using. We have successfully manufactured and used PULP based chips in the following technologies (see the IIS PULP chip gallery for more details):

  • ST Microelectronics 28nm FDSOI (both RVT and LVT)
  • GlobalFoundries 28nm SLP
  • UMC 65nm LL
  • SMIC 130nm
  • EM-Marin ALP 180nm
Even though we have tested it extensively (and still continue to do so), we can not guarantee that there are no bugs left in the system (there most probably are still several hiding). If you let us know about it, we will try to fix them as soon as it will be possible for us. The good news is that, the source code is open, you can see exactly what we did, and even figure out a solution to it (and hopefully share it with us!).
There are several ways you can contribute to the PULP project. First, reporting bugs, limitations and issues via the PULPino GitHub issue manager or our mailing list (see FAQ item) allows us to maintain the platform and make it better and more flexible. You can also propose fixes via the same mechanism. Moreover, as PULP is a research driven project, we routinely propose semester and master thesis projects in ETH Zurich and the University of Bologna. Contact us if you are interested in one of these.
We have one mailing list to share new developments and listen to change requests. You can subscribe to it by sending mail to:


subscribe pulp-info Firstname Lastname

as the subject.

Licensing and Open-Source Questions

The bulk of the PULP platform the (HDL design of its IPs, the related simulation and synthesis scripts and the IP documentation) is under copyright of ETH Zurich and the University of Bologna and is released under the Solderpad Hardware License, a liberal open-source license derived from the Apache License Version 2.0.
Most development tools we developed and software that runs on the PULP platform is released under liberal open-source licenses such as 3-clause BSD. Specialized toolchains and debug tools based on GCC are copyright of the Free Software Foundation and released under the GNU GPLv3 license.
Yes, the PULP platform is meant to be open and used by other research institutes/universities/companies. You can download it, use it directly, and even change or adapt it as you see fit. PULP is released under the Solderpad Hardware License, where we have already given this permission to everyone. Of course we are curious and would be very happy to hear from you if you are using it in your research projects.
Also, we ask you to cite the relevant scholarly publications (see ETHZ PULP page and Unibo PULP page).
Please do it, it is open and free. PULP is released under the Solderpad Hardware License, which allows commercial use and does not impose any constraint on additional IPs that you develop and connect to the platform. You can use the PULP platform, make modifications to it as you see fit, and do not need additional permission from us. Of course we are happy to hear where you are using it if you want to share!
We strongly believe in the open philosophy, and see a lot of benefits from an open release. We can more easily share our work with other research groups, we have no limitations on what we can change in the processor, and it is also good for teaching.

In addition, having a stable processing platform could help a number of small startups and SMEs to designing their own products/ICs, by reducing engineering costs. This is important, as these companies are potential employers for our graduates and we have an interest to support SMEs working on IC Design.

PULPino-specific questions

PULPino is an open-source micro-controller similar in performance to Cortex M4 but featuring the RISC-V instruction set. It is an excellent development platform for new IPs; for example, we use it to test new interfaces that we are developing. As it is a smaller platform, developing is much faster.

It is a relatively small design that easily fits on a cheap FPGA board such as a ZedBoard and can thus be used in a variety of cases where a big FPGA is too expensive (think of teaching classes!).

Finally, there are many applications where you would need a small and efficient microprocessor that will not demand a very large workload, e.g. as a small microcontroller integrated within a bigger system-on-chip. PULPino provides a ready-to-use, open source microcontroller IP that can be integrated within such designs.

Our RISC-V core supports the basic RV32CIM instruction sets. In addition, we have support for:

  1. Hardware loop instructions for more efficient loop handling;
  2. Post-increment memory instructions allowing to update pointers more efficiently;
  3. DSP like instructions enabling very energy-efficient signal processing

These can be used with the toolchain that we have customized for these functions.

Technical questions

A lot of languages! The bulk of the PULP platform is coded using the synthesizable subset of the SystemVerilog hardware description language. Software running on PULP/PULPino is written in RISC-V assembly (as little as possible!) and in C. Code running on the multi-core PULP can use the OpenMP programming model to ease parallel programming. Development tools and scripts are written in a variety of languages such C, C++, Python, TCL, and shell scripts.
Most of the IPs of the PULP platform can be used independently of one another to build a huge variety of systems, as a lot of pieces in a jigsaw puzzle (hence our logo!). While currently this connection must be done manually (as in our main PULPino repository), we provide tools to generate the simulation and synthesis scripts for the IPs automatically.
We mainly used ModelSim/QuestaSim for simulation, and that is what is also supported by our automatic script generation tools for the IPs. We cannot currently provide support on other simulation environments, but the platform should be working on any simulation tool that is able to understand synthesizable SystemVerilog. If you can provide patches to extend support for other simulation tools, we’ll be happy to review them and (if possible) merge them in.
For FPGA synthesis, we targeted mainly Xilinx FPGAs and used Xilinx Vivado, although we know that it is also possible to use Synopsys Synplify with some minor changes. We don’t expect significant problems in porting the platform to other FPGA vendors if they support SystemVerilog as a source HDL, except from adaptation of some of the IPs.
For what concerns synthesis for ASIC targets, we mainly use Synopsys Design Compiler but we expect other synthesis tools to work as well, provided that they support SystemVerilog.
Please let us know in our mailing list, and we’ll try our best to help you.