The hardware guys


Luca Benini

Benevolent Dictator for Life and overall inspirator of the PULP Platform project.

Davide Rossi

Project Leader, he is responsible for the overall architectural development and for ASIC backend implementation. He is also the main responsible for the DMA IP.

Antonio Pullini

Lead designer of all PULP external interfaces and of the uDMA subsystem. Plus, he’s the go-to person for ASIC backend implementation.

Igor Loi

Lead designer of all internal interconnect IPs and of the cluster instruction cache. He is also the responsible for frontend ASIC synthesis.

Francesco Conti

PULP “evangelist” and leader of HW acceleration and near sensor analytics efforts. He also cares about PULP emulation and maintains this website.

Michael Gautschi

He is the current lead of the PULPino project and of the development of the shared FPU/LNU. He is also one of the main designers of the OR10N and RI5CY cores.

Frank K. Gürkaynak

Main responsible for EDA tools used for PULP development, for ASIC testing and for PULP didactic usage.

Florian Zaruba

Designer of the PULPino Imperio chip, and of this website.

Michael Schaffner

Co-leader of the development of the shared FPU/LNU IPs for PULP, and main author of our logo.

Florian Glaser

Designer and maintainer of the new event unit in PULP.

Davide Schiavone

Designer of the DSP extensions for the OR10N and RI5CY cores, and the current RI5CY maintainer.

Manuele Rusci

Designer of interfaces with ultra-low power sensors, and developer of related applications.

Stefan Mach

Hail the boss of PULP boards and PCBs.

Andreas Kurth

1st Lieutenant of the group, keeper of HERO, the big PULP

Fabian Schuiki

Standard-cell memory guru, hardware designer and supreme project gitler.

Alfio Di Mauro

Event-based computing expert and tester guru in the making.

The software guys


Germain Haugou

Leader of all software integration efforts, main developer of the PULP hardware abstraction layer, runtime and SDK.

Eric Flamand

Designer of our RISC-V ISA extensions for DSP and main developer of the enhanced GCC toolchain for RI5CY.

Pirmin Vogel

Lead of all efforts to use PULP within a heterogeneous system architecture; designer of the Linux driver runtime for ARM based host systems.

Alessandro Capotondi

Co-designer of the OpenMP parallel programming runtime for PULP.

Andrea Marongiu

Co-designer of the OpenMP parallel programming runtime for PULP.

Daniele Palossi

One day he’s going to fly… PULP-based unmanned aerial vehicle aficionado.

Past members and external collaborators


Andreas Traber

Designer and main maintainer of the RI5CY core, and original designer and maintainer of PULPino.

Sven Stucki

Original designer of the porting of OR10N to the RISC-V ISA, which became the RI5CY core.

Robert Schilling

Designer of encryption HW accelerator for the PULP platform.

Renzo Andri

Original co-designer of the OR10N core.

Matthias Baer

Original co-designer of the OR10N core.