Our new PULPino release now supports four different RISC-V core configurations


With this release we are introducing Zero-riscy, a 2-level pipelined area efficient RISC-V core. In total, you will be able to select four different configurations for PULPino:
  1. RI5CY: Our standard RV32-ICM core with custom PULP extensions for DSP applications
  2. RI5CY+FPU: The RI5CY core enhanced with an IEEE-754 single precision FPU
  3. Zero-riscy: The area-efficient core that implements RV32-ICM.
  4. Micro-riscy: The even smaller core implementing RV32-EC, with 16 registers and no hardware multiplication support

We have also enhanced the PULPino environment to support all core configurations, extended the GCC toolchain, added bitstreams for the new configurations, added more tests and fixed some issues in various IPs and tests. Of course everything is freely available in System Verilog using the permissive Solderpad license.

A core for every area budget

While RI5CY is a very efficient core for DSP applications, we have received many requests for a smaller core that can be used for control applications. Zero-riscy and its even smaller brother Micro-riscy are area-optimized implementations. The synthesis results for an ASIC run on the left show an area breakdown of three configurations. Micro-riscy is 3.5x smaller than RI5CY. You can select which core configuration to use within PULPino.

Choose the core for your application

The plot shows three different application benchmarks, a DSP workload (2D-Conv), Coremark, and a control intensive application which hardly has any ALU operations (Runtime) and compares the energy consumption at low operating frequencies. As you can see, different cores perform better (lower is better) depending on the application.

What is PULPino?

PULPino is a competitive, state-of-the-art 32-bit processor based on the RISC-V architecture, with a rich set of peripherals, and full debug support. At ETH Zurich and Università di Bologna we have put many of the ideas that we have developed through our research on ultra-low-power parallel processing (PULP project) into PULPino. It is the little hip brother to its more serious bigger brothers.
You can download the entire source code, test programs, programming environment and even the bitstream for the popular ZEDboard, completely for free under the Solderpad license.

State-of-the-Art Microcontroller Core

PULPino is based on RI5CY (and Zero-riscy), optimised 32-bit RISC-V cores developed at ETH Zurich and Universita’ di Bologna. The RI5CY core has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and full support for the multiplication instruction set extension (RV32M). It implements several ISA extensions such as: hardware loops, post-incrementing load and store instructions, ALU and MAC operations, which increase the efficiency of the core in signal processing applications. Now we also support floating point (RV32M) and 16 register (RVE) configurations.

A Rich Set of I/O Peripherals

For communication with the outside world, PULPino contains a broad set of peripherals, including I2S, I2C, SPI and UART. The platform internal devices can be accessed from outside via JTAG and SPI, which allows pre-loading RAMs with executable code. In standalone mode, the platform boots from an internal boot ROM and loads its program from an external SPI flash.

Low-Power, but Powerful

To allow embedded operating systems such as FreeRTOS to run, a subset of the privileged specification is supported. Moreover, PULPino comes with many of the low-power features we developed in the PULP Project: when the core is idle, the platform can be put into a low power mode, where only a simple event unit is active and everything else is clock-gated and consumes minimal power (leakage). A specialized event unit wakes up the core in case an event/interrupt arrives.

Not a Toy Design

PULPino is a mature design: it has been taped-out as an ASIC in UMC 65nm in January 2016. The PULPino platform is available for RTL simulation as well for FPGA mapping. It has full debug support on all targets. In addition we support extended profiling with source code annotated execution times through KCacheGrind in RTL simulations and debug via GDB.

And it is free, no registration, no strings attached, you can use it, change it, adapt it, add it to your own chip, use it for classes, research, projects, products… We just ask you to acknowledge the source, and if possible, let us know what you like and what you don’t like.

Open hardware, the way it should be!

The PULPino source code is available on github, see https://github.com/pulp-platform/pulpino
For more information on PULPino and PULP see our websites: http://pulp.ethz.ch and  http://www-micrel.deis.unibo.it/pulp-project/