We are releasing three major updates to PULPino!

We are ready to release three major updates of the PULPino platform:

  1. a patch to the RISC-V toolchain that will allow all extensions in PULPino to be used
  2. an upgraded core with vector extensions
  3. full debug support including a GDB debug bridge

More in detail, this major update includes a patch to the original RISC-V toolchain that supports all extensions we have added to the RISC-V core including:

  • vector ALU instructions
  • hardware loops
  • post increment load/store instructions
  • full support for the RV32IMC instruction set, with a prefetch buffer for compressed instructions and support of all M extensions (including divisions)
  • new DSP extensions working on vectors of 4 bytes or 2 half-words (e.g. dot product)
  • fixed-point arithmetic support
  • support for Memory-Mapped Input/Output (MMIO) debug, which allows to fully debug applications running PULPino with GDB (yes, you can also use Eclipse!)

What is PULPino?

PULPino is a competitive, state-of-the-art 32-bit processor based on the RISC-V architecture, with a rich set of peripherals, and full debug support. At ETH Zurich and Università di Bologna we have put many of the ideas that we have developed through our research on ultra-low-power parallel processing (PULP project) into PULPino. It is the little hip brother to its more serious bigger brothers.
You can download the entire source code, test programs, programming environment and even the bitstream for the popular ZEDboard, completely for free under the Solderpad license.

State-of-the-Art Microcontroller Core

PULPino is based on RI5CY, an optimised 32-bit RISC-V core developed at ETH Zurich and Universita’ di Bologna. The core has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and full support for the multiplication instruction set extension (RV32M). It implements several ISA extensions such as: hardware loops, post-incrementing load and store instructions, ALU and MAC operations, which increase the efficiency of the core in signal processing applications.

A Rich Set of I/O Peripherals

For communication with the outside world, PULPino contains a broad set of peripherals, including I2S, I2C, SPI and UART. The platform internal devices can be accessed from outside via JTAG and SPI, which allows pre-loading RAMs with executable code. In standalone mode, the platform boots from an internal boot ROM and loads its program from an external SPI flash.

Low-Power, but Powerful

To allow embedded operating systems such as FreeRTOS to run, a subset of the privileged specification is supported. Moreover, PULPino comes with many of the low-power features we developed in the PULP Project: when the core is idle, the platform can be put into a low power mode, where only a simple event unit is active and everything else is clock-gated and consumes minimal power (leakage). A specialized event unit wakes up the core in case an event/interrupt arrives.

Not a Toy Design

PULPino is a mature design: it has been taped-out as an ASIC in UMC 65nm in January 2016. The PULPino platform is available for RTL simulation as well for FPGA mapping. It has full debug support on all targets. In addition we support extended profiling with source code annotated execution times through KCacheGrind in RTL simulations and debug via GDB.

And it is free, no registration, no strings attached, you can use it, change it, adapt it, add it to your own chip, use it for classes, research, projects, products… We just ask you to acknowledge the source, and if possible, let us know what you like and what you don’t like.

Open hardware, the way it should be!

The PULPino source code is available on github, see https://github.com/pulp-platform/pulpino
For more information on PULPino and PULP see our websites: http://pulp.ethz.ch and  http://www-micrel.deis.unibo.it/pulp-project/